Embark on a journey of knowledge! Take the quiz and earn valuable credits.
Challenge yourself and boost your learning! Start the quiz now to earn credits.
Unlock your potential! Begin the quiz, answer questions, and accumulate credits along the way.
Embark on a journey of knowledge! Take the quiz and earn valuable credits.
Challenge yourself and boost your learning! Start the quiz now to earn credits.
Unlock your potential! Begin the quiz, answer questions, and accumulate credits along the way.
+10 pts
What is Service Request Block mean?
A Service Request Block (SRB) is a data structure of MVS/370 and successor versions of IBM mainframe operating systems employed mainly, but not exclusively, by the Start Input/Output interface.
An SRB may be considered, in the abstract, to be a highly optimized Task Control Block (TCB), one which has few, if any, associated resources other than access to the processor itself. All system resources which are utilized under an SRB must be accessed through the use of "branch entries", some of which are new entries to traditional system services which were formerly accessed exclusively using SVC instructions (which an SRB may not employ for any purpose other than abnormally terminating itself in which case SVC 13, ABEND, may be used, however the "branch entry" to ABTERM is really more appropriate).
When employed by the Start Input/Output interface, an SRB is always paired with an Input/Output Supervisor Block (IOSB).
When otherwise employed, an SRB facilitates inter-address-space communication in general, and inter-application communication in particular.
SRBs may also be employed for intra-address-space processes, where the highest possible performance is required, and in this case the necessary resources are first acquired under a TCB (usually the "job step" TCB), before the SRBs are SCHEDULEd (i.e., are presented to the system dispatcher to compete for processor resources).
It is conceivable that an address space may have but one TCB (again, the "job step" TCB) but tens or hundreds or even thousands of SRBs, with the SRBs performing almost all of the work in the address space, and the TCB merely synchronizing the SRBs and responding to communications from the system operator.
For purposes of such synchronization, the TCB will usually issue a WAITR, SVC 1, specifying a list of Event Control Blocks (ECBs; one ECB per SRB, plus one for the system operator), and each SRB will indicate its completion to the TCB by using a "branch entry" to the POST system service (which is normally SVC 2, but in this special case would be a call to the address contained in CVT0PT01), and specifying the ECB which is associated with its SRB, and possibly a "message" to the TCB. The "message", should it be present, is often placed in the lowest 24 bits of the ECB, and which is otherwise unused. The highest eight bits are used by the system.
Disk device access and network device access is available to SRBs using the "improved control interval processing" feature of VSAM and the "fast path" feature of VTAM, respectively.
referencePosted on 18 Oct 2024, this text provides information on Miscellaneous in Computing related to Computing. Please note that while accuracy is prioritized, the data presented might not be entirely correct or up-to-date. This information is offered for general knowledge and informational purposes only, and should not be considered as a substitute for professional advice.
Turn Your Knowledge into Earnings.
Ever curious about what that abbreviation stands for? fullforms has got them all listed out for you to explore. Simply,Choose a subject/topic and get started on a self-paced learning journey in a world of fullforms.
OPEN APP
Click "Allow Notifications" in Your Browser to Access Quiz and Earn Rewards! 🚀
Write Your Comments or Explanations to Help Others